1. Field of the Invention
The present invention relates to a semiconductor device which includes an extensive evaluation device constituted in a semiconductor substrate and a method of fabricating the same.
2. Description of the Background Art
Recently it has been a customary practice in the mass production of semiconductor devices to control a mass production line by evaluating the finish of produced semiconductor elements.
FIG. 22 illustrates a method of evaluating devices by means of TEGs (test element groups). Some TEGs 14 (e.g., three TEGs in FIG. 22) are suitably disposed on a mass-produced wafer 13. The TEGs 14 are adapted to be capable of measuring process parameters such as current amplification factor, resistance, breakdown voltage of pn junctions and threshold voltage of transistors. The finish of the semiconductor elements made on the wafer 13 is evaluated by the inspection of the TEGs 14.
FIG. 23 illustrates a method of evaluating devices by means of monitoring transistors. A single wafer process monitoring transistor 15 is incorporated in each integrated circuit (IC) chip 1 made on the wafer 13.
FIG. 24 illustrates the details of the IC chip 1 shown in FIG. 23. Wirings 18 make electrical connections between standard cell blocks 17 each of which is composed of a plurality of standard cells fabricated according to the standard cell approach. The monitoring transistor 15 is formed on the IC chip 1 in a region where the standard cell blocks 17 and wirings 18 are not formed. Electrodes of the monitoring transistor 15 are electrically connected to transistor evaluation pads 16 through monitoring wirings 19. The stylus of an external tester is brought into contact with the transistor evaluation pads 16 for the inspection of the characteristics of the monitoring transistor 15.
FIG. 25 is a plan view of the monitoring transistor 15, and FIG. 26 is a cross-sectional view taken along the line A--A of FIG. 25. Reference numeral 65 designates an n-type epitaxial region; 66 designates a p-type diffusion region; and 67 designates an n-type diffusion region. Thus the monitoring transistor 15 is an npn bipolar transistor which includes the n-type epitaxial region 65 serving as a collector, the p-type diffusion region 66 serving as a base and the n-type diffusion region 67 serving as an emitter. The finish of the semiconductor elements incorporated in the IC chip 1 is evaluated by the inspection of the electric characteristics of the sampled monitoring transistor.
The conventional semiconductor devices are, as above mentioned, provided with the TEGs for evaluating practical semiconductor elements on the IC chip and with the monitoring transistors.
However, the method in which the TEGs are incorporated in the wafer has a problem in that the fabrication scatter within the wafer surface is not considered in the evaluation.
The method in which the single monitoring transistor is mounted on each IC chip also has a problem. At LSI levels, since a thousand to a hundred thousand transistors are constituted on one IC chip, the monitoring transistors are too small in number as compared with the transistors to be actually fabricated to be used as satisfactory samples. This method has a limit in accurate evaluation of the practical semiconductor elements.